Explorations in Application of Machine Learning in Pre-Synthesis Power Estimation of Digital Systems

Abstract

This paper presents an approach to exploit Machine Learning (ML) to accurately and efficiently predict power consumption in digital systems at the higher-levels of abstraction prior to synthesis. As valuable resources and much time are invested when developing new products, designers can greatly benefit to know early in the design process if the final design's power consumption is within the reasonable margins of the given constraints. This is done by analyzing the high-level models of the design (behavioral or register transfer level) and without investing resources for synthesizing the design. We have used machine learning models trained on tallies of cell groups that were parsed from gate-level netlists in order to estimate the design’s “internal”, “switching”, “leakage”, and “total” powers. Four supervised learning models, Multi-Layer Perceptron (MLP), Ridge Regression, Elastic Net, and K-Nearest Neighbors, were evaluated across three different technologies: 90 nm, 45 nm, and 15 nm cell libraries. Our experiments provide a meaningful comparison of these models for the 3 technology nodes. The most successful model in the 15 nm library was MLP, which had the smallest error in predicting total power. Additionally, MLP models improved the average error when predicting a single power component (internal, switching, or leakage), compared to simultaneously predicting all three power components in a single model.