A Higher-Level Synthesis Tool for Rapid-Prototyping of Verilog RTL Designs from FSMD Specifications

Abstract

This work presents a light-weight synthesis tool, F2VGen (Finite State Machine to Verilog Generator), that generates Register Transfer Level (RTL) implementations modeled using Verilog hardware description language (HDL) from abstract specifications provided as extended finite state machines (FSMD). This approach takes synthesis yet to a higher level. In contrast to conventional high-level synthesis (HLS) where the design specification is given in behavioral Verilog, in this work specification begins at an even higher level of abstraction and is provided as a finite state machine that captures the data-flow. Designers can input the design specification using a graphical interface (GUI). The resulting synthesized design is implemented at the register-transfer level and is distinctly divided into a data-path (that performs the computations) and a controller (that controls the operation of the data-path). The process does not guarantee an optimized implementation in terms of area, power consumption or speed. However, it realizes the required functionality in hardware, and can be used in many settings where access to a fast prototype is required. The prototypes are implemented in reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) and present an effective solution when a fast proof of concept design is needed, and also as a stand-in model in situations when testing the interactive systems in actual hardware is required.