DeepSPICE: Accelerating Digital Cell Characterization Using Deep Learning
DOI:
https://doi.org/10.47611/jsrhs.v11i3.3375Keywords:
deep learning, digital design, integrated circuits, machine learning, timing analysis, standard cell, MOSFETAbstract
This paper introduces DeepSPICE, a machine learning approach to accelerate the characterization of the building blocks, or cells, of digital integrated circuits. In contrast to the current approach of computing the input-to-output propagation delays of a cell by simulating all possible input event combinations, DeepSPICE employs a Deep Neural Network (DNN) to learn from the propagation delays obtained by simulating a small subset of input event combinations and to predict those for the rest. The DNN for training and prediction is created using the Keras framework, and Python is used for automating the entire flow. The effectiveness of the DeepSPICE approach is demonstrated on 14 CMOS logic cells with the number of inputs ranging from 2 to 7. Simulations to create the training set for each cell are performed using the open source NGSPICE circuit simulator on their transistor-level circuit descriptions. Experiments using two different train:test ratios of 0.25:0.75 and 0.3:0.7 demonstrate the promise of reduction in time with DeepSPICE, especially for large cells where simulation costs are expensive. For cells with at least 6 inputs, DeepSPICE computes propagation delays for all input event combinations 2 to 2.2 times faster than baseline while limiting the error between 6.3% and 12.3%.
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References or Bibliography
Batten, Christopher. ECE 5745 Complex Digital ASIC Design. https://www.csl.cornell.edu/courses/ece5745/handouts/ece5745-T05-methodology-auto.pdf.
Černý, David, and Josef Dobeš. “Deep Learning Neural Network Algorithm for Computation of Spice Transient Simulation of Nonlinear Time Dependent Circuits.” Electronics, vol. 11, no. 1, 2021, p. 15., https://doi.org/10.3390/electronics11010015.
Lee, Chuan-Zheng. Transistors. https://web.stanford.edu/class/archive/engr/engr40m.1178/slides/transistors.pdf.
NGSPICE: Circuit Simulator - Oregon State University. https://web.engr.oregonstate.edu/~traylor/ece391/smith_NGSPICE_USERGUIDE_ECE391.pdf.
“PrimeSim HSPICE the Gold Standard for Accurate Circuit Simulation.” The Gold Standard for Accurate Circuit Simulation, https://www.synopsys.com/implementation-and-signoff/ams-simulation/primesim-hspice.html.
“Spectre Simulation Platform.” Cadence, https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design/circuit-simulation/spectre-simulation-platform.html.
Tan, Wei-Lii. “Machine Learning Overcomes Library Challenges at the Latest Process Nodes.” Tech Design Forum Techniques, https://www.techdesignforums.com/practice/technique/machine-learning-overcomes-library-challenges-at-newer-process-nodes/.
“What Is Library Characterization? – How It Works & Techniques.” Synopsys, https://www.synopsys.com/glossary/what-is-library-characterization.html.
Designing Combinational Logic Gates in CMOS. http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter6.pdf.
MOS Transistors, CMOS Logic Circuits - Stanford University. https://web.stanford.edu/class/archive/engr/engr40m.1178/slides_sp17/lecture08.pdf
The Spice Home Page. http://bwrcs.eecs.berkeley.edu/Classes/IcBook/SPICE/
Mentor, ST team on chip process characterisation. (2020, November 20). Eenewseurope.Com. https://www.eenewseurope.com/en/mentor-st-team-on-chip-process-characterisation/
Nowe, Philip. “Timing (Analysis) is Everything – A How-To Guide for Timing Analysis.” Circuit Cellar, https://circuitcellar.com/wp-content/uploads/2015/07/CC160-Nowe.pdf
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